1. Field of the Invention
The present invention relates to a semiconductor memory having memory cells made of such components as ferroelectric capacitors which retain logical values of data in the form of electric charges. In particular, the present invention relates to a circuit technology for reading data from the memory cells.
2. Description of the Related Art
There has been recently proposed a technique for reading a ferroelectric memory, referred to as bit line GND sensing technique (disclosed in Japanese Unexamined Patent Application Publication No. 2002-133857 and IEEE Journal of Solid-State Circuits, Vol. 37, No. 5, pp. 592-598, May 2002). According to this type of reading technique, in order to prevent a variance in voltage of bit lines, at voltage appliance to plate lines charges are read out from memory cells to the bit lines and are transferred to charge storing circuits through charge transferring circuits referred to as charge transfers which are formed in pre-sense amplifiers. The logical values of the data retained in the memory cells are determined in accordance with the amounts of charges transferred to the charge storing circuits. The charge transfers are made of pMOS transistors. The gate-to-source voltages of the pMOS transistors are initialized to the same value as their threshold voltage before the rise of the plate lines. The gates of the pMOS transistors are controlled by inverting amplifiers which lower their output voltages in accordance with the rise of the bit lines in voltage.
In a read operation, the gate-to-source voltages of the pMOS transistors are initialized to the threshold voltage. Then, the pMOS transistors remain ON weakly till the rise of the plate lines. Consequently, the pMOS transistors have leakage between their sources and drains. The leakage causes an increase in the drain voltages (negative voltages) of the pMOS transistors, which causes a problem of a decrease in read margin.
In addition, the activation periods of control signals that activate the inverting amplifiers have been conventionally created by using delay circuits or the like. Because of this, the activation periods of the control signal need be designed to deal with the worst values of the operating temperature and operating voltage. Thus, the activation periods of the inverting amplifiers have been unnecessarily longer, consuming power in vain. Since the inverting amplifiers need be provided for each of the pre-sense amplifiers, and a large number of them operate simultaneously, they greatly affects the amount of the power consumption.